Analog circuits frequently include high voltage components such as drain extended metal oxide semiconductor (DEMOS) transistors and buried collector bipolar transistors which operate above 100 volts and integrated circuits (ICs) with advanced complementary metal oxide semiconductor (CMOS) digital circuits, for example 180 nm and 65 nm CMOS logic and static random access memory (SRAM). It is desirable to integrate the high voltage components into the ICs to reduce analog circuit cost and complexity. High voltage components require junctions with wide depletion regions and shallow doping gradients to avoid premature breakdown and/or shortened operating lifetime, which are typically achieved using long anneals of ion implanted regions at high temperatures. However, fabrication of advanced CMOS circuits requires dimensional stability to within a few nanometers, which precludes long anneals at high temperatures. Furthermore, ICs containing advanced CMOS circuits typically have relatively thin buried layers under relatively thin epitaxial layers, compared to analog high voltage ICs. Components including buried layers with high doping densities for low electrical resistances are prone to low breakdown potentials when built with typical advanced CMOS fabrication process sequences. Adding deep well regions around buried layers to increase breakdown potentials undesirably adds considerable area to an integrated high voltage component.
Accordingly, an architecture for devices with buried layers that can operate above 100 volts in ICs built with typical advanced CMOS fabrication process sequences is desired.